The present invention relates to an integrated circuit having a processor and or integrated memory to be suitably accessed from an external device and a system utilizing the integrated circuit.
Conventionally, in a single-chip microcomputer (MC68705R 3: Motorola; Prior art example 1) comprising an integrated nonvolatile memory, memory addresses are sequentially supplied to the integrated memory based on the memory address beforehand set in a bootstrap or the like under control of CPU disposed in the large scale integrated circuit (to be referred to as LSI herebelow) and data externally inputted is stored in an area of the memory at the specified address or data is outputted therefrom to an external device.
In the prior art example 1, the address of the integrated memory is supplied by the control section of the CPU, hence an external device cannot access an arbitrary memory area by specifying its memory address.
In another microcomputer (8749: Intel; Prior art example 2), a CPU disposed in the LSI comprises an internal bus shared among an internal memory, processing elements, an instruction register, a status register, a timer and counter, and a program counter, wherein a memory address externally specified for the internal memory is supplied from the program counter of the CPU connected to the internal bus and the data is accessed therethrough.
In the prior art example 2, the internal bus of the CPU is operated in a time shared manner to access the memory address and data. Control of the time-shared internal bus includes functions such as a function for discriminating information from other circuits from the memory address and data, a function for inhibiting the other circuits to access the internal bus while the data in an area at the specified memory address is being accessed, and a function for synchronizing the input/output of an external data, for example, for executing the input/output of the data whose length is at least four times the internal clock.
Consequently, in order to access the internal memory from an external device, it is required to operate an internal logic of the CPU and to execute the input/output of the memory address and data with the external device under conditions which satisfy the internal logic.
When a memory integrated in a single-chip microcomputer is accessed from an device externally located with respect to the LSI as described above, it is necessary to operate the internal logic of the CPU and to match the timing in the prior art example 2; therefore, discrete memory LSI's, for example, memory programming equipments such as EPROM programmers in which data is stored by specifying an arbitrary memory address cannot be utilized, which leads to a problem that a customized memory programming equipment satisfying the interface conditions for the operation of the logic in the CPU is required.
In addition, when a configuration, for example, a distributed processing system for executing an independent job in each LSI or a multiprocessor system with a common data base is processed by use of a plurality of LSI's, it is necessary to operate the internal logic of the CPU and to match the timing in the prior art example 2, hence an external control mechanism must be added to the LSI, which brings forth a problem that the conditions for interfacing the LSI become more complicated.